IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
If handshaking is employed, the control signals cts_n/enrx_n are deasserted while the receive
register has valid unread data. The cts_n/enrx_n signal is reasserted after the data in the receive
register is read. The value of the SP0RD and SP1RD registers is undefined at reset (see
Table 39).
Table 39. Serial Port Receive Registers
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
RDATA
Bits [15–8]—Reserved.
Bits [7–0]—RDATA → Holds valid data while the RDR bit of the respective status
register is set.
5.1.24 SP0TD (084h) and SP1TD (014h)
Serial Port Transmit Registers. Data is written to these registers by software with the values to
be transmitted by the serial port. Double buffering of these transmitters allows for the
transmission of data from the transmit shift registers (no software access), while the next data are
written into the transmit registers.
The TEMT and THRE bits in the respective Serial Port Status registers indicate the status of
these two pairs of registers.
Invoking handshaking requires that rts_n/rtr_n inputs be asserted before the transmitters can send
any data which remain held in the transmit and shift registers without affecting the transmit pin.
The value of the SPTD registers is undefined at reset (see Table 40).
Table 40. Serial Port Transmit Registers
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
TDATA
Bits [15–8]—Reserved.
Bits [7–0]—TDATA → Holds the data to be transmitted.
5.1.25 SP0STS (082h) and SP1STS (012h)
Serial Port Status Register. These registers store information concerning the current status of the
respective ports. The value of the SP0STS and SP1STS registers is undefined at reset (see
Table 41).
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