IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
The width of the data bus for the lcs_n space should be configured in the AUXCON register
before activating the lcs_n chip select pin, by any write access to the LMCS register. The value
of the LMCS register is undefined at reset except DA, which is set to 0 (see Table 35).
Table 35. Low-Memory Chip Select Register
15 14 13 12 11 10
UB2–UB0
9
1
8
1
7
6
5
1
4
1
3
1
2
1
0
0
1
1
DA PSE
R2 R1-R0
Bit [15]—Reserved. Set to 0.
Bits [14–12]—UB [2–0] → Upper Boundary. These bits define the upper boundary of
memory accessed by the lcs_n chip select. The LMCS Block-Size Programming Values
shown below list the possible block-size configurations (a 512-Kbyte maximum).
LMCS Block-Size Programming Values
Memory
Ending
Block Size Address UB2–UB0
64K
0FFFFh
1FFFFh
3FFFFh
7FFFFh
000b
001b
011b
111b
128K
256K
512K
Bits [11–8]—Reserved. Set to 1.
Bit [7]—DA Disable Address → When set to 1, the address bus is disabled, providing
some measure of power saving. When 0, the address is driven onto the address bus
ad15–ad0 during the address phase of a bus cycle. This bit is set to 0 at reset.
– If bhe_n/aden_n is held at 0 during the rising edge of res_n, the address bus is always
driven, regardless of the setting of DA.
Bit [6]—PSE PSRAM Mode Enable → When set to 1, PSRAM support for the lcs_n chip
select memory space is enabled. The EDRAM, MDRAM, and CDRAM RCU registers
must be configured for auto refresh before PSRAM support is enabled. Setting the
enable bit (EN) in the enable RCU register (EDRAM, offset e4h) configures the
mcs3_n/rfsh_n as rfsh_n.
Bits [5–3]—Reserved. Set to 1.
Bit [2]—R2 Ready Mode → When set to 1, the external ready is ignored. When 0, it is
required. The value of these bits determines the number of wait states inserted.
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