IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Table 41. Serial Port Status Register
15 14 13 12 11
Reserved
10
9
8
7
6
5
4
3
2
1
0
BRK1 BRK0 RB8 RDR THRE FER OER PER TEMT HS0 Res
Bits [15–11]—Reserved.
Bit [10]—BRK1 Long Break Detected → A long break is a low signal level on the rxd
pin for a period greater that 2M + 3 bit times, where:
M = start bit + number of data bits + parity bits + stop bit
(Equation 3)
– Should data reception be in progress when the break starts, the reception of the
current word will be completed and the timing for the break will begin. Because the
stop bit will not be detected due to the break, this will generate a framing error.
– Detection of the break with the 2M + 3 bit time period can only be guaranteed if the
break commences outside of a frame.
Note: This bit should be reset by software.
Bit [9]—BRK0 Short Break Detected → A short break is a low on the rxd pin for a
period greater than M bit times (see Equation 3 above).
– Should data reception be in progress when the break starts, the reception of the
current word will be completed and the timing for the break will begin. Because the
stop bit will not be detected due to the break, this will generate a framing error.
– Detection of the break with the M bit time period can only be guaranteed if the break
commences outside of a frame.
Note: This bit should be reset by software.
Bit [8]—RB8 Received Bit [8] → This is the ninth data bit received in modes 2 and 3
(see Section 5.1.26, SP0CT (080h) and SP1CT (010h)).
Note: This bit should be reset by software.
Bit [7]—RDR Receive Data Ready → When this bit is 1, it indicates that the respective
SPRD register contains valid data. This is a read-only bit and can be reset only by
reading the corresponding receive register.
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