IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Table 79. Read Cycle Timing
a
a
No.
Name
Description
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
10
0
–
–
General Timing Responses
3
4
5
6
8
9
tCHSV
tCLSH
tCLAV
tCLAX
tCHDX
tCHLH
Status Active Delay
0
0
0
0
0
0
6
6
Status Inactive Delay
ad Address Valid Delay
Address Hold
12
12
–
Status Hold Time
ale Active Delay
8
10 tLHLL
11 tCHLL
12 tAVLL
13 tLLAX
14 tAVCH
15 tCLAZ
16 tCLCSV
17 tCXCSX
18 tCHCSX
19 tDXDL
20 tCVCTV
21 tCVDEX
22 tCHCTV
23 tLHAV
99 tPLAL
ale Width
tCLCH-5
–
ale Inactive Delay
0
8
ad Address Valid to ale Low
ad Address Hold from ale Inactive
ad Address Valid to Clock High
ad Address Float Delay
mcs_n/pcs_n Inactive Delay
mcs_n/pcs_n Hold from Command Inactive
mcs_n/pcs_n Inactive Delay
den_n Inactive to dt/r_n Low
Control Active Delay 1
den_n Inactive Delay
tCLCH
–
tCHCL
–
0
–
0
12
12
–
0
tCLCH
0
0
12
–
0
10
9
0
Control Active Delay 2
ale High to Address Valid
pcs Low to ale Low
0
10
–
7.5
–
tCLCH
Read Cycle Timing Responses
24 tAZRL
25 tCLRL
26 tRLRH
27 tCLRH
28 tRHLH
29 tRHAV
41 tDSHLH
59 tRHDX
66 tAVRL
67 tCHCSV
68 tCHAV
ad Address Float to rd_n Active
0
0
–
10
–
rd_n Active Delay
rd_n Pulse Width
tCLCL
0
rd_n Inactive Delay
10
–
rd_n Inactive to ale High
rd_n Inactive to ad Address Active
ds_n Inactive to ale Inactive
rd_n High to Data Hold on ad Bus
a Address Valid to rd_n Low
clkouta High to lcs_n/usc_n Valid
clkouta High to a Address Valid
tCLCH
tCLCL
tCLCH
0
–
–
–
tCLCL+tCHCL
–
9
8
0
0
a
In nanoseconds.
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