XMC4500
XMC4000 Family
Electrical Parameters
3.3.7
Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions apply.
Table 38
SWD Interface Timing Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ. Max.
SWDCLK clock period
tSC SR 25
40
–
–
–
–
–
–
–
ns
ns
CL = 30 pF
CL = 50 pF
SWDCLK high time
SWDCLK low time
t1 SR 10
t2 SR 10
500000 ns
500000 ns
SWDIO input setup
t3 SR
6
–
ns
to SWDCLK rising edge
SWDIO input hold
t4 SR
6
–
–
ns
after SWDCLK rising edge
SWDIO output valid time t5 CC
after SWDCLK rising edge
–
–
3
–
–
–
17
13
–
ns
ns
ns
CL = 50 pF
CL = 30 pF
SWDIO output hold time t6 CC
from SWDCLK rising edge
tSC
t1
t2
SWDCLK
t6
SWDIO
(Output)
t5
t3
t4
SWDIO
(Input)
Figure 17
SWD Timing
Data Sheet
70
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
