XC835/836
Electrical Parameters
3.2.4
Flash Memory Parameters
The XC835/836 is delivered with all Flash sectors erased (read all zeros).
The data retention time of the XC835/836’s Flash memory (i.e. the time after which
stored data can still be retrieved) depends on the number of times the Flash memory has
been erased and programmed.
Note: Flash memory parameters are not subject to production test but verified by design
and/or characterization.
Table 12
Flash Timing Parameters (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Remarks
Min. Typ. Max.
Read access time
(per byte)
Programming time
(per wordline)
Erase time
(one or more sectors)
tACC
tPR
CC –
CC –
CC –
125
–
–
–
ns
2.2
ms
ms
tER
120
Flash wait states
NWSFLASH CC
0
1
CPU clock = 8 MHz
CPU clock = 24 MHz
Table 13
Retention
20 years
5 years
2 years
2 years
Flash Data Retention and Endurance (Operating Conditions apply)
Endurance1)
1,000 cycles
10,000 cycles
70,000 cycles
100,000 cycles
Size
up to 8 Kbytes
1 Kbyte
512 bytes
128 bytes
Remarks
1) One cycle refers to the programming of all wordlines in a sector and erasing of sector. The Flash endurance
data specified in Table 13 is valid only if the following conditions are fulfilled:
- the maximum number of erase cycles per Flash sector must not exceed 100,000 cycles.
- the maximum number of erase cycles per Flash bank must not exceed 300,000 cycles.
- the maximum number of program cycles per Flash bank must not exceed 2,500,000 cycles.
Data Sheet
33
V1.2, 2011-03
INFINEON [ Infineon ]
