XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
4.4.5
External Bus Timing
The following parameters define the behavior of the XC228x’s bus interface.
Table 20
CLKOUT Reference Signal
Symbol
Parameter
Limits
Max.
Unit
Min.
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
tc5
tc6
tc7
tc8
tc9
CC
40/25/151)
ns
ns
ns
ns
ns
CC
CC
CC
CC
3
3
–
–
–
–
3
3
1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to fCPU = 25/40/66 MHz).
For longer periods the relative deviation decreases (see PLL deviation formula).
tC9
tC8
tC5
tC6
tC7
CLKOUT
MCT05571
Figure 19
CLKOUT Signal Timing
Note: The term CLKOUT refers to the reference clock output signal which is generated
by selecting fSYS as source signal for the clock output signal EXTCLK on pin P2.8
and by enabling the high-speed clock driver on this pin.
Data Sheet
93
V0.91, 2007-02
Draft Version
INFINEON [ Infineon ]
