Preliminary
16/32-Bit Single-Chip Microcontroller with 32-Bit
Performance
XC228x
XC2000 Family
1
Summary of Features
For a quick overview or reference, the XC228x’s properties are listed here in a
condensed way.
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High Performance 16-bit CPU with 5-Stage Pipeline
– 15 ns Instruction Cycle Time at 66 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle 32-bit Addition and Subtraction with 40-bit Result
– 1-Cycle Multiplication (16 × 16 bit)
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Background Division (32 / 16 bit) in 21 Cycles
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
16-Priority-Level Interrupt System with up to 87 Sources, Selectable External Inputs
for Interrupt Generation and Wake-Up, Sample-Rate down to 15 ns
8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
Clock Generation from Internal or External Clock Sources,
via on-chip PLL or via Prescaler
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On-Chip Memory Modules
– 1 Kbyte On-Chip Stand-By RAM (SBRAM)
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 16 Kbytes On-Chip Data SRAM (DSRAM)
– Upt to 64 Kbytes On-Chip Program/Data SRAM (PSRAM)
– Up to 768 Kbytes On-Chip Program Memory (Flash Memory)
On-Chip Peripheral Modules
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– Two Synchronizable A/D Converters with a total of 24 Channels, 10-bit Resolution,
Conversion Time down to 1.2 µs, Optional Data Preprocessing (Data Reduction,
Range Check)
– 16-Channel General Purpose Capture/Compare Unit (CAPCOM2)
– Up to four Capture/Compare Units for flexible PWM Signal Generation (CCU6x)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Six Serial Interface Channels to be used as UART, LIN, High-Speed Synchronous
Channel (SPI/QSPI), IIC Bus Interface (10-bit addressing, 400 kbit/s), IIS Interface
Data Sheet
4
V0.91, 2007-02
Draft Version
INFINEON [ Infineon ]
