OPTIREG™ SBC TLE9274QXV33
Supervision functions
13.3
VS power on reset
When powering up, the device detects the VS power on reset when VS > VPOR,r, and the SPI bit POR is set to
indicate that all SPI registers are set to POR default settings. The buck regulator starts up. The reset output is
kept LOW and is only released when VCC1 has exceeded VRT1,r and after tRD1 has elapsed.
If VS < VPOR,f, an internal reset is generated and the SBC is switched OFF. The SBC will restart in INIT mode when
VS > VPOR,r rising. Timing behavior is shown in Figure 43.
VS
VPOR,r
VPOR,f
t
t
VCC1
VRT1,r
The reset threshold can be
configured via SPI in SBC
Normal Mode, default is VRT1
VRTx,f
RO
SBC Restart Mode is
entered whenever the
Reset is triggered
t
tRD1
SBC Mode
Re-
start
SBC OFF
SBC INIT MODE
Any SBC MODE
SBC OFF
t
SPI
Command
Figure 43 Ramp up/down example of supply voltage
13.4
Undervoltage VLIN
When the supply voltage VLIN reaches the undervoltage threshold (VLIN,UVD) the SBC does the following
actions:
•
The SPI bit VLIN_UV is set. No other error bits are set. The bit can be cleared once the condition is no longer
present
•
LIN is set to LIN Receive-Only mode
For additional information, please refer to Chapter 9.2.7.
Datasheet
90
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
