OPTIREG™ SBC TLE9274QXV33
High-speed CAN transceiver
8.2.6
Bus dominant clamping
If the HS CAN bus signal is dominant for a time t > tBUS_CAN_TO, in CAN Normal and Receiver-only mode, a bus
dominant clamping is detected and the SPI bit CAN_FAIL is set. The transceiver configuration stays
unchanged.
8.2.7
VCAN undervoltage detection
The voltage at the VCAN supply pin is monitored in CAN Normal and Receive-Only mode. If the HS CAN
transceiver is set in CAN Wake-Capable mode, the VCAN supply pin is enable after that a valid WUP is detected.
In case of VCAN undervoltage a signalization via SPI bit VCAN_UV is triggered and the TLE9274QXV33 disables
the transmitter stage. If the CAN supply reaches a higher level than the under voltage detection threshold
(VCAN > VCAN_UV), the transceiver is automatically switched back to CAN Normal mode. The transceiver
configuration stays unchanged.
Datasheet
52
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
