OPTIREG™ SBC TLE9274QXV33
System features
5.1.7
SBC Development mode
The SBC Development mode is used during development phase of the application, especially for software
development. The mode is reached by setting the FO3/TEST pin to LOW when the device is in SBC Init mode
and by sending an arbitrary SPI command. The SBC Init mode is reached after the power-up.
When sending a software reset, it is no longer possible to enter SBC Development mode.
The software reset is the SPI command that set the MODE bits in M_S_CTRL register.
SBC Development mode can only be left by a power-down while FO3/TEST pin is high or open, or by setting
the MODE bits on M_S_CTRL SBC Software Reset regardless of the state of FO3/TEST.
In this mode, the watchdog does not need to be triggered. No reset is triggered because of watchdog failure.
When the FO3/TEST pin is left open, or connected to VS during the start-up, the SBC starts into normal
operation. The FO3 pin has an integrated pull-up resistor, RTEST, (switched ON only during SBC Init mode) to
prevent the SBC device from starting in SBC Development mode during normal life of the vehicle.
Datasheet
26
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
