TLE9263QX
System Features
5.1.5
SBC Restart Mode
There are multiple reasons to enter the SBC Restart Mode. The purpose of the SBC Restart Mode is to reset the
microcontroller:
•
•
•
in case of under voltage on VCC1 in SBC Normal and in SBC Stop Mode,
in case of over voltage on VCC1 if the bit VCC1_OV_RST is set and if CFGP = ‘1’,
due to 1st incorrect Watchdog triggering (only if Config1, Config3 or Config 4 is selected, otherwise SBC Fail-
Safe Mode is immediately entered),
•
In case of a wake event from SBC Sleep or SBC Fail-Safe Mode or a release of over temperature shutdown
(TSD2) out of SBC Fail-Safe Mode this transition is used to ramp up VCC1 after a wake in a defined way.
From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode, i.e the mode is left automatically by
the SBC without any microcontroller influence. The SBC MODE bits are cleared. As shown in Figure 48 the Reset
Output (RO) is pulled low when entering Restart Mode and is released at the transition to Normal Mode after the
reset delay time (tRD1). The watchdog timer will start with a long open window starting from the moment of the rising
edge of RO and the watchdog period setting in the register WD_CTRL will be changed to the respective default
value ‘100’.
Leaving the SBC Restart Mode will not result in changing / deactivating the Fail outputs.
The behavior of the blocks is listed below:
•
All FOx outputs are activated in case of a 1st watchdog trigger failure (if Config1 or Config2 is selected) or
in case of VCC1 over voltage detection (if VCC1_OV_RST is set)
•
•
•
•
VCC1 is ON or ramping up
VCC2 will be disabled if it was activated before
VCC3 is fixed or ramping as configured in SBC Normal Mode
CAN is “woken” due to a wake event or OFF depending on previous SBC and transceiver mode (see also
Chapter 10). It is wake capable when it was in CAN Normal-, Receive Only or wake capable mode before SBC
Restart Mode
•
LIN is “woken” or OFF depending on previous SBC and transceiver mode (see also Chapter 11). It is wake
capable when it was in LIN Normal-, Receive Only or wake capable mode before SBC Restart Mode.
•
•
•
•
HS Outputs will be disabled if they were activated before
RO is pulled low during SBC Restart Mode
SPI communication is ignored by the SBC, i.e. it is not interpreted
The Restart Mode entry is signalled in the SPI register DEV_STAT with the bits DEV_STAT
Table 7
Reasons for Restart - State of SPI Status Bits after Return to Normal Mode
Prev. SBC Mode
Normal
Normal
Normal
Normal
Stop
Event
DEV_STAT WD_FAIL VCC1_UV VCC1_OV VCC1_SC
1x Watchdog Failure
2x Watchdog Failure
01
01
01
10
xx
xx
01
10
xx
xx
xx
x
x
1
x
x
x
1
x
x
x
x
x
1
x
x
x
1
x
x
x
x
x
x
x
x
x
x
VCC1 under voltage reset 01
VCC1 over voltage reset 01
1x Watchdog Failure
2x Watchdog Failure
01
01
Stop
Stop
VCC1 under voltage reset 01
VCC1 over voltage reset 01
Stop
Sleep
Wake-up event
Wake-up event
10
01
Fail-Safe
see “Reasons for Fail Safe, Table 8”
Data Sheet
28
Rev. 1.1, 2014-09-26
INFINEON [ Infineon ]
