TLE9263QX
System Features
5.1
Block Description of State Machine
The different SBC Modes are selected via SPI by setting the respective SBC MODE bits in the register
M_S_CTRL. The SBC MODE bits are cleared when going through SBC Restart Mode and thus always show the
current SBC mode.
First battery connection
SBC Soft Reset
SBC Init Mode
*
Config.: settings can be
(Long open window)
changed in this SBC mode ;
Cyc. Sense
OFF
VCC1
ON
VCC2
OFF
CAN(3)
OFF
VCC3
OFF Config.
LINx(3)
OFF
WD
Fixed: settings stay as defined
in SBC Normal Mode
Any SPI
command
Cyc. Wake
OFF
FOx
inact.
HSx
OFF
* The SBC Development Mode
is a super set of state machine
where the WD timer is stopped
and CAN/LINx behavior differs
in SBC Init Mode . Otherwise,
there are no differences in
behavior.
SBC Normal Mode
Cyc. Sense
config.
VCC1
ON
VCC2
VCC3
WD
WD trigger
config.
config. config.
CAN(3)
config.
Cyc.Wake
config.
FOx
act/inact
LINx(3)
config. config.
HSx
ꢀ
ꢀ
Reset is released
WD starts with long open window
Automatic
SPI cmd
SPI cmd
SPI cmd
SBC Stop Mode
SBC Sleep Mode
VCC3(2)
VCC1
ON
VCC2
fixed
VCC3
fixed
WD
fixed
Cyc. Sense
fixed
VCC1
OFF
VCC2
WD
OFF.
Cyc. Sense
fixed
Fixed /
fixed
OFF
VCC1 over voltage
Config 1/3 (if VCC_OV_RST set)
CAN
LINx
Wake
capable/off
FOx
fixed
CAN
fixed
LINx
fixed
HSx
fixed
Cyc.Wake
fixed
FOx
fixed
HSx
fixed
Cyc. Wake
OFF
Wake
capable/off
Wake up event
SBC Restart Mode
(RO pin is asserted)
Watchdog Failure:
Config 1/3 & 1st WD failure
in Config4
VCC3(2)
After 4x consecutive VCC1
under voltage events
(if VS > VS_UV)
VCC1
ON/
VCC2
OFF
WD
OFF
Cyc. Sense
OFF
VCC1 over voltage
Config 2/4 (if VCC_OV_RST set)
fixed/
ramping
ramping
FOx(5)
active/
fixed
CAN (4) LINx (4)
HSx
OFF
Cyc.Wake
OFF
woken /
OFF
woken /
VCC1
Undervoltage
OFF
SBC Fail-Safe Mode (1)
TSD2 event,
1st Watchdog Failure Config 2,
2nd Watchdog Failure, Config 4
Cyc. Sense
OFF
VCC1
OFF
VCC2
OFF
VCC3
OFF
WD
OFF
CAN, LINx, WKx wake-up event
OR
Release of over temperature
TSD2 after tTSD2
FOx(5)
active
HSx
OFF
CAN
Wake
capable
LINx
Wake
capable
(1) After Fail-Safe Mode entry, the device will stay for at least typ . 1s
in this mode (with RO low) after a TSD2 event and min. typ. 100ms
after other Fail-Safe Events. Only then the device can leave the
mode via a wake-up event. Wake events are stored during this time.
Cyc.Wake
OFF
VCC1 Short to GND
(2) according to VCC3 configuration
(3) For SBC Development Mode CAN/LINx/VCC2 are ON in SBC Init
Mode and stay ON when going from there to SBC Normal Mode
(4) See chapter CAN & LIN for detailed behavior in SBC Restart Mode
(5) See Chapter5.1.5 and 14.1 for detailed FOx behavior
Figure 3
State Diagram showing the SBC Operating Modes
Data Sheet
21
Rev. 1.1, 2014-09-26
INFINEON [ Infineon ]
