TLE 6244X
detected the data byte ’00h’ is transmitted to the controller after having sent the verification
byte (even if bit INSW afterwards is wrong) but modifications on any register of TLE6244 are
not allowed until bit INSW is valid, too.
If an invalid instruction is detected bit TRANS_F in the following verification byte is set to
’High’. This bit must not be cleared before it has been sent to the microcontroller.
6) If TLE6244X and additional IC’s are connected to one common slave select, they are
distinguished by the chip address (CPAD1, CPAD0). If an IC with 32bit-transmission-format is
selected, TLE6232 must not be activated, even if slave select is set to ’low’ and
the first two bits of the third byte of the 32bit-transmission are identical to the chip address
of TLE6244X.
During the transmission of CPAD1 and CPAD0 the data output SO remains in tristate (see
timing diagram of the SPI in chapter 3.9. ).
SPI access format:
WRITE-access (16bit)
READ-access (16bit)
8 bit command + 8bit data
8 bit command + 8bit data
SS
SI
SS
SI
SPI instruction
MSB
Data 8bit
SPI instruction
MSB
XX XX XX XX
Data 8bit
MSB
Check byte
ZZ + 6bit
00 00 00 00
Check byte
ZZ + 6bit
SO
SO
MSB
Z=tristate
Verification byte:
MSB
7
6
Z
5
1
4
0
3
1
2
0
1
1
0
Z
TRANS_F
Bit
Name
TRANS_F
Description
0
Bit = 1: error detected during previous transfer
Bit = 0: previous transfer was recognised as valid
State after reset: 0
1
2
3
4
5
6
7
Fixed to High
Fixed to Low
Fixed to High
Fixed to Low
Fixed to High
send as high impedance
send as high impedance
Final Data Sheet
11
V4.2, 2003-08-29
INFINEON [ Infineon ]
