TLD7002-16ES 参数 Datasheet PDF下载

型号：	TLD7002-16ES
PDF下载：	下载PDF文件查看货源
内容描述：	[The TLD7002-16ES is a 16 channel device with integrated and protected output stages. It is designed to control LEDs with a current up to 76.5 mA as linear current sink (LCS). The power stages can be configured in parallel for higher load currents. Each individual power output stage is configured to a 6-bit current set value stored in the OTP. 16 independent and individual PWM configurations can be set. A high-speed lighting interface is used for device OTP programming, configuration, control and]
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文件页数/大小：	82 页 / 3105 K
品牌：	INFINEON [ Infineon ]

TLD7002-16ES

Datasheet

7 Load Diagnostic

Load Diagnostic

Features

7.1

Several load diagnostic features are integrated in the device for all of the output channels OUTn:

•

Open load detection (OL)

Forward voltage warning to detect short to supply

Single LED Short detection (SLS)

Short between two adjacent output channels

Digital feedback of VS, GPINn, VLED, min(VOUTn) and VFWDn

ERRn feedback, if enabled

Configurable fault management, reporting, latching or retry behavior

7.2

VFWD measurement

The device provides an analog to digital conversion of V_FWDvoltage with a resolution of n_VRES,Hi, accessible with the

HSLI interface when OUTn pulse width (t_OUTnPW) fulfills:

•

t_OUTnPW> t_{diag_dly}+ t_{DIAG_ON}in case phase shif is enabled OR

t_OUTnPW> t_{diag_dly}+ N * t_{DIAG_ON}in case phase shif is disabled, where N is equal to the number of

preceding channels with phase shif disabled.

V_FWDis defined as V_LED-V_OUTor V_S-V_OUTdepending on the load configuration stored in the OTP. All 16 V_FWDvoltage

measurements are sampled sequentially starting from OUT0 to OUT15. One channel starts sampling afer t_{diag_dly}and

the result is available afer t_{DIAG_ON}as shown in the Figure 13.

In case of phase shif disabled between two adjacent channels, the t_{diag_dly}is skipped.

The phase shif shall be set to t_phs> t_{diag_dly}+ 2*t_{DIAG_ON}for proper supplies and output voltages sampling.

The conversion is done once per PWM period and continuously updated. New data is signaled with a dedicated VALID

flag which is reset afer reading completion.

Figure 13

Timing diagram for ON-state diagnostics synchronized to the PWM

7.3

VGPIN measurement

The device provides an analog to digital conversion of V_GPINvoltage with a resolution of n_VRES,Lo, accessible with the

HSLI interface. The device samples the V_GPInand stores the result in a VGPIN register. New data is signaled with a

dedicated VALID flag which is reset afer reading completion.

Note: The sampling period depends on the phase-shif configuration according to following table.

Datasheet

Rev.1.00

2022-05-03