TDA5235
Functional Description
The following handling mechanism for read-clear registers was chosen due to
implementation of the Burst Read command:
• the current Interrupt Status (ISx) register 8-bit content is latched into the SPI shift
register after the last address bit is clocked-in (point A in Figure 58)
• the IS register is then cleared after last IS register bit is clocked out of the SPI
interface (point B in Figure 58)
Consequence: any interrupt event occurring in the window-time between points A and B
is cleared at point B and not stored/shown in an later readout of ISx.
(However: NINT signal is toggling in any case, if occurring interrupt is not masked in IMx
register)
A
B
8-bit @2MHz = 4us
irq2 (masked?)
irq1 (masked?)
nint
ncs
read/readb data = IS(t+0)
SPI IF
inst
addr
read/capture IS*
content
SFR IS* read clear
@end of data frame
SFR IS* IS(t-1)
IS(t+0)
IS(t+1) 0x00
NOTE:
SFR IS(j) status flag is cleared
before it can be read if an IRQ
occurs during SPI data frame
Figure 58
ISx Readout Set Clear Collision
Please see also the IMPORTANT NOTE in the Burst Read section !
Data Sheet
88
V1.0, 2010-02-19
INFINEON [ Infineon ]
