TDA5235
Appendix
Register Description
Field
Bits
Type
Description
WUPMSEL
5
w
Wake Up Pattern Mode Selection
0B
1B
Chip mode
Bit mode
Reset: 0H
WULCUFFB
UFFBLCOO
4
3
w
w
Select a "Wake Up on Level Criterion", when UFFBLCOO is enabled.
0B
1B
RSSI
automatically selected, when A_CHCFG.EXTPROC = "10"
Signal Recognition
Reset: 0H
Ultrafast Fall Back to SLEEP or additional Level criterion in
Constant On Off.
Enables additional parallel processing of "Level Criterion", when a "Data
Criterion" is selected in WUCRT.
In case of Fast Fall Back to SLEEP or Permanent Wake-Up Search, this
mode is called UFFB (Ultrafast Fall Back). Same Mode can be used in
Constant On-Off.
0B
1B
Disabled
Enabled
Reset: 0H
WUCRT
2:0
w
Select a "Wake Up Criterion"
000B Pattern Detection (Data Criterion)
When A_CHCFG.EXTROC = "01" this setting is mapped to 0x3
001B Random Bits (Data Criterion)
When A_CHCFG.EXTROC = "01" this setting is mapped to 0x3
010B Equal Bits (Data Criterion)
When A_CHCFG.EXTROC = "01" this setting is mapped to 0x3
011B Wake Up on Symbol Sync, Valid Data Rate (Data Criterion); The
A_WUBCNT Register is
not used in this mode
100B RSSI (Level Criterion)
automatically selected, when A_CHCFG.EXTPROC = "10"
101B Signal Recognition (Level Criterion)
110B n.u.
111B n.u.
Reset: 4H
Wake-Up Pattern Register 0
A_WUPAT0
Offset
018H
Reset Value
00H
Wake-Up Pattern Register 0
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:83$7ꢀ
Z
Data Sheet
189
V1.0, 2010-02-19
INFINEON [ Infineon ]
