TC1796
Functional Description
3.2
On-Chip Memories
As shown in the TC1796 block diagram on Page 10, some of the TC1796 units provide
on-chip memories that are used as program or data memory.
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Program memory in PMU and PMI
– 2 Mbyte on-chip Program Flash (PFLASH)
– 16 Kbyte Boot ROM (BROM)
– 48 Kbyte Scratch-Pad RAM (SPRAM)
– 16 Kbyte Instruction Cache (ICACHE)
Data memory in DMU, PMU and DMI
– 56 Kbyte Local Data RAM (LDRAM)
– 8 Kbyte Dual-port RAM (DPRAM)
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– 64 Kbyte Data Memory (SRAM)
– 16 Kbyte data memory (SBRAM) for standby operation during power-down
– 128 Kbyte on-chip Data Flash (DFLASH)
Memory of the PCP2
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– 32 Kbyte Code Memory (CMEM)
– 16 Kbyte Parameter Memory (PRAM)
On-chip SRAMs with parity error detection
Features of the Program Flash
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2 Mbyte on-chip program Flash memory
Usable for instruction code execution or constant data storage
256-byte wide program interface
– 256 bytes are programmed into PFLASH page in one step/command
256-bit read interface
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– Transfer from PFLASH to CPU/PMI by four 64-bit single-cycle burst transfers
Dynamic correction of single-bit errors during read access
Detection of double bit errors
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Fixed sector architecture
– Eight 16 Kbyte, one 128 Kbyte, one 256 Kbyte, and three 512 Kbyte sectors
– Each sector separately erasable
– Each sector separately write-protectable
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Configurable read protection for complete PFLASH with sophisticated read access
supervision, combined with write protection for complete PFLASH (protection against
“Trojan horse” software)
Configurable write protection for each sector
– Each sector separately write-protectable
– With capability to be re-programmed
– With capability to be locked forever (OTP)
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Password mechanism for temporarily disable write or read protection
On-chip programming voltage generation
PFLASH is delivered in erased state (read all zeros)
Data Sheet
37
V1.0, 2008-04
INFINEON [ Infineon ]
