TC1796
Electrical Parameters
1) This parameter is valid under assumption that PORST signal is constantly at low level during the power-
up/power-down of the VDDP
.
2) tOSCS is defined from the moment when VDDOSC3 = 3.13V until the oscillations reach an amplitude at XTAL1 of
0,3*VDDOSC3. This parameter is verified by device characterization. The external oscillator circuitry must be
optimized by the customer and checked for negative resistance as recommended and specified by crystal
suppliers.
3) Any HDRST activation is internally prolonged to 1024 FPI bus clock (fSYS) cycles.
4) Applicable for input pins TESTMODE, TRST, BRKIN, and TXD1A with noise suppression filter of PORST
switched-on (BYPASS = 0).
5) The setup/hold values are applicable for Port 0 and Port 10 input pins with noise suppression filter of HDRST
switched-on (BYPASS = 0), independently whether HDRST is used as input or output.
6) fSYS = fCPU/2
7) Not subject to production test, verified by design / characterization.
8) This parameter includes the delay of the analog spike filter in the PORST pad.
9) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first
user instruction has entered the CPU and its processing starts.
10) The duration of the boot time is defined between the following events:
1. Hardware reset: the falling edge of a short HDRST pulse and the moment when the first user instruction
has entered the CPU and its processing starts, if the HDRST pulse is shorter than 1024 × TSYS
.
If the HDRST pulse is longer than 1024 × TSYS, only the time beyond the 1024 × TSYS should be added to the
boot time (HDRST falling edge to first user instruction).
2. Software reset: the moment of starting the software reset and the moment when the first user instruction
has entered the CPU and its processing starts
Data Sheet
110
V1.0, 2008-04
INFINEON [ Infineon ]
