TC1796
Electrical Parameters
2) Parameter test correlation for VDDEBU = 2.5 V ± 5%
4.3.3
Power Sequencing
There is a restriction for the power sequencing of the 3.3 V domain including VDDEBU as
shown in Figure 29: it must always be higher than 1.5 V domain - 0.5 V. The grey area
shows the valid range for V3.3V and VDDEBU relative to an exemplary 1.5 V ramp.
V
DDP, VDDOSC3, VDDFL3, VDDM, VDDMF belong to the 3.3 V power supply domain, that is
referenced in Figure 29 as V3.3. The VDDM and VDDMF sub domains are connected with
anti parallel ESD protection diodes in TC1796 design steps BC and BD. The VDDM
,
V
DDMF, VDDP, VDDOSC3 sub domains are connected with anti parallel ESD protection
diodes in TC1796 design step BE.
VDD, VDDOSC and VDDAF belong to the 1.5 V power supply domain, referenced as V1.5.
V
DDEBU belongs to its own 2.5V to 3.3V domain.
3.3V
V3.3, VDDEBU
V1.5
1.5V
V3.3, VDDEBU > V1.5 - 0.5V
Time
VDDP
(3.3V)
PORST
Time
PowerSeq 2
Figure 29
VDDP / VDDEBU / VDD Power Up Sequence
All ground pins VSS must be externally connected to one single star point in the system.
The difference voltage between the ground pins must not exceed 200 mV.
The PORST signal must be activated at latest before any power supply voltage falls
below the levels shown on the figure below. In this case, only the memory row of a Flash
memory that was a target of a write at the moment of the power loss will contain
unreliable content. Additionally, the PORST signal should be activated as soon as
possible. The sooner the PORST signal is activated, the less time the system operates
outside of the normal operating power supply range.
Data Sheet
107
V1.0, 2008-04
INFINEON [ Infineon ]
