TC39x BC/BD-Step
Pin Definition and Functions: LFBGA-516 Package Variant Pin Configuration
Table 2-7 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F16
P13.3
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN0_3
Mux input channel 0 of TIM module 3
PU1 /
VEXT /
ES6
GTM_TIM2_IN0_3
Mux input channel 0 of TIM module 2
General-purpose output
GTM muxed output
P13.3
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT94
ASCLIN10_ASLSO
Slave select signal output
Master SPI data output (LVDS P line)
Reserved
QSPI2_MTSRP
—
MSC0_SOP
Data output - direct part of the differential signal
Reserved
—
—
Reserved
B16
P13.4
LVDS_TX General-purpose input
/ FAST /
GTM_TIM6_IN0_4
Mux input channel 0 of TIM module 6
PU1 /
VEXT /
ES6
GTM_TIM5_IN3_4
Mux input channel 3 of TIM module 5
Mux input channel 3 of TIM module 3
General-purpose output
GTM muxed output
GTM_TIM3_IN3_8
P13.4
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT253
—
Reserved
—
Reserved
MSC2_EN0
Chip Select
MSC2_FCLN
Shift-clock inverted part of the differential signal
Reserved
—
CAN23_TXD
CAN transmit output node 3
A16
P13.5
LVDS_TX General-purpose input
/ FAST /
GTM_TIM6_IN1_4
Mux input channel 1 of TIM module 6
PU1 /
VEXT /
ES6
GTM_TIM5_IN4_4
Mux input channel 4 of TIM module 5
Mux input channel 4 of TIM module 3
CAN receive input node 3
General-purpose output
GTM muxed output
GTM_TIM3_IN4_9
CAN23_RXDD
P13.5
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT254
—
Reserved
—
Reserved
—
Reserved
MSC2_FCLP
Shift-clock direct part of the differential signal
Reserved
—
—
Reserved
Data Sheet
68
V 1.2, 2021-03
OPEN MARKET VERSION
INFINEON [ Infineon ]
