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SAK-TC399XP-256F300S BC 参数 Datasheet PDF下载

SAK-TC399XP-256F300S BC图片预览
型号: SAK-TC399XP-256F300S BC
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内容描述: [Infineon releases its second generation AURIX microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontrol­ler. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. ]
分类和应用:
文件页数/大小: 548 页 / 21256 K
品牌: INFINEON [ Infineon ]
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TC39x BC/BD-Step  
Pin Definition and Functions: LFBGA-516 Package Variant Pin Configuration  
Table 2-7 Port 13 Functions (cont’d)  
Ball  
Symbol  
Ctrl. Buffer  
Type  
Function  
F17  
P13.1  
I
LVDS_TX General-purpose input  
/ FAST /  
GTM_TIM3_IN6_3  
GTM_TIM2_IN6_3  
I2C0_SCLB  
CAN10_RXDD  
ASCLIN10_ARXD  
P13.1  
Mux input channel 6 of TIM module 3  
PU1 /  
VEXT /  
ES6  
Mux input channel 6 of TIM module 2  
Serial Clock Input 1  
CAN receive input node 0  
Receive input  
O0  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
I
General-purpose output  
GTM muxed output  
GTM_TOUT92  
Reserved  
QSPI2_SCLKP  
Master SPI clock output (LVDS P line)  
Reserved  
MSC0_FCLP  
I2C0_SCL  
Shift-clock direct part of the differential signal  
Serial Clock Output  
Reserved  
G16  
P13.2  
LVDS_TX General-purpose input  
/ FAST /  
GTM_TIM3_IN7_3  
GTM_TIM2_IN7_3  
GPT120_CAPINA  
Mux input channel 7 of TIM module 3  
PU1 /  
VEXT /  
ES6  
Mux input channel 7 of TIM module 2  
Trigger input to capture value of timer T5 into CAPREL  
register  
I2C0_SDAB  
P13.2  
Serial Data Input 1  
O0  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
General-purpose output  
GTM_TOUT93  
ASCLIN10_ASCLK  
QSPI2_MTSRN  
MSC0_FCLP  
MSC0_SON  
I2C0_SDA  
GTM muxed output  
Shift clock output  
Master SPI data output (LVDS N line)  
Shift-clock direct part of the differential signal  
Data output - inverted part of the differential signal  
Serial Data Output  
Reserved  
Data Sheet  
67  
V 1.2, 2021-03  
OPEN MARKET VERSION  
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