TC39x BC/BD-Step
Pin Definition and Functions: LFBGA-516 Package Variant Pin Configuration
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F11
P10.3
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN6_10
GTM_TIM1_IN3_3
GTM_TIM0_IN3_3
QSPI1_MTSRA
SCU_E_REQ3_0
Mux input channel 6 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Slave SPI data input
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T5INB
P10.3
Trigger/gate input of timer T5
General-purpose output
GTM muxed output
Monitor input 2
O0
O1
GTM_TOUT105
IOM_MON2_10
—
O2
O3
O4
O5
O6
Reserved
QSPI1_MTSR
MSC0_EN0
—
Master SPI data output
Chip Select
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O7
I
Reserved
G11
P10.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Slave SPI data input
Hall capture input 0
Trigger/gate input of core timer T3
Receive input
GTM_TIM4_IN7_3
GTM_TIM1_IN6_2
GTM_TIM0_IN6_2
QSPI1_MTSRC
CCU60_CCPOS0C
GPT120_T3INB
ASCLIN11_ARXB
P10.4
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
GTM_TOUT106
IOM_MON2_11
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI1_SLSO8
QSPI1_MTSR
MSC0_EN0
—
Master slave select output
Master SPI data output
Chip Select
Reserved
—
Reserved
Data Sheet
50
V 1.2, 2021-03
OPEN MARKET VERSION