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    SAK-TC399XP-256F300S BC 参数 Datasheet PDF下载

    SAK-TC399XP-256F300S BC图片预览
    型号： SAK-TC399XP-256F300S BC
    PDF下载： 下载PDF文件 查看货源
    内容描述： [Infineon releases its second generation AURIX microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontrol­ler. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. ]
    分类和应用：
    文件页数/大小： 548 页 / 21256 K
    品牌： INFINEON [ Infineon ]
     浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第469页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第470页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第471页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第472页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第474页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第475页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第476页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第477页  
    TC39x BC/BD-Step  
    Electrical SpecificationSystem Phase Locked Loop (SYS_PLL)  
    3.16  
    System Phase Locked Loop (SYS_PLL)  
    Table 3-36 PLL System  
    Parameter  
    Symbol  
    Values  
    Typ.  
    Unit  
    Note / Test Condition  
    Min.  
    10  
    Max.  
    40  
    DCO Input frequency range  
    Modulation Amplitude  
    Peak Period jitter  
    f
    REF CC  
    -
    -
    -
    MHz  
    %
    MA CC  
    DP CC  
    0
    2
    -200  
    200  
    ps  
    without modulation  
    (PLL output frequency)  
    Peak Accumulated Jitter  
    Total long term jitter  
    D
    PP CC  
    -5  
    -
    -
    -
    5
    ns  
    ns  
    without modulation  
    J
    TOT CC  
    11.5  
    including modulation;  
    MA 1.25%; fREF 20MHz  
    System frequency deviation  
    DCO frequency range  
    PLL lock-in time  
    f
    f
    SYSD CC  
    DCO CC  
    -
    -
    -
    -
    0.01  
    800  
    100  
    %
    with active modulation  
    400  
    4
    MHz  
    µs  
    tL CC  
    Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the  
    maximum driver and sharp edge.  
    Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of  
    V
    PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.  
    These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the  
    supply pins and using PCB supply and ground planes.  
    Data Sheet  
    473  
    V 1.2, 2021-03  
    OPEN MARKET VERSION  

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