TC1767
Introduction
MRSTA
MRSTB
MTSR
fSSC
fCLC
Master
Clock
Control
MTSR
MTSRA
MTSRB
MRST
Slave
Slave
MRST
Address
Decoder
SCLKA
SCLKB
SCLK
SSC
Module
(Kernel)
Port
Control
RIR
TIR
EIR
Master
Slave
SCLK
SLSI[7:1]
Interrupt
Control
SLSI[7:1]
SLSO[7:0]
SLSOANDO[7:0]
SLSOANDI[7:0]
SLSO[7:0]
SLSOANDO[7:0]
Master
DMA Requests
Enable
M/S Select
MCB06058_mod
Figure 6
General Block Diagram of the SSC Interface
The SSC supports full-duplex and half-duplex serial synchronous communication up to
40 Mbit/s (@ 80 MHz module clock, Master Mode). The serial clock signal can be
generated by the SSC itself (Master Mode) or can be received from an external master
(Slave Mode). Data width, shift direction, clock polarity and phase are programmable.
This allows communication with SPI-compatible devices. Transmission and reception of
data are double-buffered. A shift clock generator provides the SSC with a separate serial
clock signal. One slave select input is available for slave mode operation. Eight
programmable slave select outputs (chip selects) are supported in Master Mode.
Data Sheet
32
V1.3, 2009-09
INFINEON [ Infineon ]
