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SAK-TC1767-256F133HL 参数 Datasheet PDF下载

SAK-TC1767-256F133HL图片预览
型号: SAK-TC1767-256F133HL
PDF下载: 下载PDF文件 查看货源
内容描述: 32位单芯片微控制器 [32-Bit Single-Chip Microcontroller]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 126 页 / 832 K
品牌: INFINEON [ Infineon ]
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TC1767  
Introduction  
2.4.3  
Micro Second Channel Interface  
The Micro Second Channel (MSC) interface provides serial communication links  
typically used to connect power switches or other peripheral devices. The serial  
communication link includes a fast synchronous downstream channel and a slow  
asynchronous upstream channel. Figure 7 shows a global view of the interface signals  
of the MSC interface.  
fMSC  
Clock  
Control  
fCLC  
FCLP  
FCLN  
SOP  
SON  
EN0  
Address  
Decoder  
MSC  
Module  
(Kernel)  
SR[3:0]  
16  
Interrupt  
Control  
EN1  
4
EN2  
To DMA  
EN3  
ALTINL[15:0]  
ALTINH[15:0]  
EMGSTOPMSC  
8
SDI[7:0]  
16  
MCB06059  
Figure 7  
General Block Diagram of the MSC Interface  
The downstream and upstream channels of the MSC module communicate with the  
external world via nine I/O lines. Eight output lines are required for the serial  
communication of the downstream channel (clock, data, and enable signals). One out of  
eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The  
source of the serial data to be transmitted by the downstream channel can be MSC  
register contents or data that is provided on the ALTINL/ALTINH input lines. These input  
lines are typically connected with other on-chip peripheral units (for example with a timer  
unit such as the GPTA). An emergency stop input signal makes it possible to set bits of  
the serial data stream to dedicated values in an emergency case.  
Clock control, address decoding, and interrupt service request control are managed  
outside the MSC module kernel. Service request outputs are able to trigger an interrupt  
or a DMA request.  
Data Sheet  
34  
V1.3, 2009-09  
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