TC1767
Introduction
fASC
Clock
Control
RXD
TXD
RXD
TXD
Address
Decoder
ASC
Module
(Kernel)
Port
Control
EIR
TBIR
TIR
RIR
Interrupt
Control
To DMA
MCB05762_mod
Figure 5
General Block Diagram of the ASC Interface
The ASC provides serial communication between the TC1767 and other
microcontrollers, microprocessors, or external peripherals.
The ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In Synchronous Mode, data is transmitted or received
synchronous to a shift clock that is generated by the ASC internally. In Asynchronous
Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
provides the ASC with a separate serial clock signal, which can be accurately adjusted
by a prescaler implemented as fractional divider.
Data Sheet
30
V1.3, 2009-09
INFINEON [ Infineon ]
