C167CR
C167SR
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
T5EUD
fCPU
T5IN
2n : 1
T5
Mode
Control
U/D
Interrupt
Request
GPT2 Timer T5
Clear
Capture
Interrupt
Request
T3
MUX
CT3
CAPIN
GPT2 CAPREL
Interrupt
Request
GPT2 Timer T6
U/D
T6OTL
T6OUT
T6IN
T6
Mode
Control
Other
Timers
fCPU
2n : 1
T6EUD
MCB03999
n = 2 … 9
Figure 7
Block Diagram of GPT2
Data Sheet
27
V3.2, 2001-07