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SAK-C167CR-LM 参数 Datasheet PDF下载

SAK-C167CR-LM图片预览
型号: SAK-C167CR-LM
PDF下载: 下载PDF文件 查看货源
内容描述: 16位单芯片微控制器 [16-Bit Single-Chip Microcontroller]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 74 页 / 954 K
品牌: INFINEON [ Infineon ]
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C167CR  
C167SR  
CAN-Module  
The integrated CAN-Module handles the completely autonomous transmission and  
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),  
i.e. the on-chip CAN-Module can receive and transmit standard frames with 11-bit  
identifiers as well as extended frames with 29-bit identifiers.  
The module provides Full CAN functionality on up to 15 message objects. Message  
object 15 may be configured for Basic CAN functionality. Both modes provide separate  
masks for acceptance filtering which allows to accept a number of identifiers in Full CAN  
mode and also allows to disregard a number of identifiers in Basic CAN mode. All  
message objects can be updated independent from the other objects and are equipped  
for the maximum message length of 8 bytes.  
The bit timing is derived from the XCLK and is programmable up to a data rate of 1 Mbit/  
s. The CAN-Module uses two pins of Port 4 to interface to an external bus transceiver.  
Note: When the CAN interface is to be used the segment address output on Port 4 must  
be limited to 4 bits, i.e. A19 A16. This is necessary to enable the alternate  
function of the CAN interface pins.  
Watchdog Timer  
The Watchdog Timer represents one of the fail-safe mechanisms which have been  
implemented to prevent the controller from malfunctioning for longer periods of time.  
The Watchdog Timer is always enabled after a reset of the chip, and can only be  
disabled in the time interval until the EINIT (end of initialization) instruction has been  
executed. Thus, the chips start-up procedure is always monitored. The software has to  
be designed to service the Watchdog Timer before it overflows. If, due to hardware or  
software related failures, the software fails to do so, the Watchdog Timer overflows and  
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow  
external hardware components to be reset.  
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2  
or by 128. The high byte of the Watchdog Timer register can be set to a prespecified  
reload value (stored in WDTREL) in order to allow further variation of the monitored time  
interval. Each time it is serviced by the application software, the high byte of the  
Watchdog Timer is reloaded. Thus, time intervals between 15.5 µs and 254 ms can be  
monitored (@ 33 MHz).  
The default Watchdog Timer interval after reset is 3.97 ms (@ 33 MHz).  
Data Sheet  
30  
V3.2, 2001-07  
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