C167CR
C167SR
Note: When the on-chip CAN Module is to be used the segment address output on
Port 4 must be limited to 4 bits (i.e. A19 … A16) in order to enable the alternate
function of the CAN interface pins. CS lines can be used to increase the total
amount of addressable external memory.
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C167CR’s instructions can be
executed in just one machine cycle which requires 60 ns at 33 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a
16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another
pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
CPU
16
Internal
RAM
SP
STKOV
STKUN
MDH
MDL
R15
Exec. Unit
Instr. Ptr.
Instr. Reg.
Mul/Div-HW
Bit-Mask Gen
General
Purpose
Registers
R15
ALU
32
4-Stage
Pipeline
(16-bit)
ROM
Barrel - Shifter
Context Ptr.
R0
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
16
R0
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Page Ptr.
Code Seg. Ptr.
MCB02147
Figure 4
CPU Block Diagram
Data Sheet
16
V3.2, 2001-07
INFINEON [ Infineon ]
