C167CR
C167SR
Functional Description
The architecture of the C167CR combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C167CR.
Note: All time specifications refer to a CPU clock of 33 MHz
(see definition in the AC Characteristics section).
C166-Core
ProgMem
IRAM
Internal
RAM
16
16
Data
Data
32
16
ROM
128/32
KByte
Instr. / Data
CPU
2 KByte
XTAL
Osc / PLL
WDT
XRAM
PEC
External Instr. / Data
2 KByte
16-Level
Priority
Interrupt Controller
16
Interrupt Bus
Peripheral Data Bus
16
CAN
Rev 2.0B active
ADC ASC0 SSC
GPT PWM CCOM2CCOM1
10-Bit
(USART)
(SPI)
T2
T3
T4
T7
T0
16
Channels
EBC
T8
T1
8
8
XBUS Control
External Bus
Control
16
T5
T6
BRGen
BRGen
Port 0
Port 1
Port 5
Port 3
Port 7
8
Port 8
8
16
16
16
15
Figure 3
Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resources, the X-Peripherals (see Figure 3).
Data Sheet
13
V3.2, 2001-07
INFINEON [ Infineon ]
