SAB 82525
SAB 82526
SAF 82525
SAF 82526
Transmit FIFO (WRITE) XFIFO (00. . .1F/40. . .5F)
Interrupt Mode
selected if DMA bit in XBCH is reset.
Up to 32 bytes of transmit data can be written to the XFIFO following an XPR interrupt.
DMA Mode
selected if DMA bit in XBCH is set.
Prior to any data transfer, the actual byte count of the frame to be transmitted must be written
to the XBCH, XBCL registers by the user.
If data transfer is then initiated via the CMDR register (command XTF or XIF), the HSCX
autonomously requests the correct amount of block data transfers (n × 32 + REST, n = 0, 1, …).
Note: Addresses within the address space of the FIFO’s are interpreted equally, i.e. the actual
data byte can be accessed with any address within the valid scope.
Semiconductor Group
81
INFINEON [ Infineon ]
