SAB 82525
SAB 82526
SAF 82525
SAF 82526
8.2 Register Definitions
Receive FIFO (Read) RFIFO (00. . .1F/40. . .5F)
Interrupt Controlled Data Transfer (Interrupt Mode)
selected if DMA bit in XBCH is reset.
Up to 32 bytes of receive data can be read from the RFIFO following an RPF or an RME
interrupt.
RPF Interrupt: Exactly 32 bytes to be read.
RME Interrupt: Number of bytes to be determined by reading the RBCL, RBCH registers.
DMA Controlled Data Transfer (DMA Mode)
selected if DMA bit in XBCH
If the RFIFO contains 32 bytes, the HSCX autonomously requests a block data transfer by
DMA activating the DRQR line as long as the start of the 32nd read cycle. This forces the DMA
controller to continuously perform bus cycles till 32 bytes are transferred from the HSCX to the
system memory, (level triggered, demand transfer mode of DMA controller).
If the RFIFO contains less than 32 bytes (one short frame or the last of a long frame) the HSCX
requests a block data transfer depending on the contents of the RFIFO according to the
following table:
RFIFO
DMA
Contents
(Bytes)
Request
(Bytes)
1, 2, 3
4 - 7
4
8
8 - 15
16 - 32
16
32
Additionally an RME interrupt is issued after the last byte has been transferred.
As a result, the DMA controller may transfer more bytes as actually valid in the current received
frame. The valid byte count must therefore be determined by reading the RBCH, RBCL
registers following the RME interrupt.
Semiconductor Group
80
INFINEON [ Infineon ]
