SAB 82525
SAB 82526
SAF 82525
SAF 82526
After the DMA controller has been set up for the reception of the next frame, the CPU must be
issue a RMC command to acknowledge the completion of the receive frame processing.
The HSCX will not initiate further DMA cycles by activating the DRQR line prior to the reception
of RMC.
Note: It’s also possible to set up the DMA controller immediately after the start of a frame has
been detected using the HSCX’s RFS (Receive Frame Start) interrupt option (see
chapter 4.3).
The following figure gives an example of a DMA controlled reception sequence, supposed that
a long frame (66 bytes) followed by two short frames (6 bytes each) are received.
Receive Frame 1
(66 Bytes)
RF2
6
RF3
6
32
32
2
Serial
Interface
HSCX
CPU/DMA
Interface
DRQR(32)
DRQR(32)
DRQR(4)
DRQR(8)
DRQR(8)
. . .
. . .
. . .
. . .
. . .
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RME RMC
RME RMC
RME RMC
ITD00252
DMA Read Cycles (68)
Figure 38
DMA Driven Reception Sequence Example
Semiconductor Group
78
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