SAB 82525
SAB 82526
SAF 82525
SAF 82526
EXA … Extended Interrupt of Channel A (Channel B only)
An interrupt is caused by channel B and source(s) is (are) indicated in the EXIR register of
channel B.
Note: The ICA, EXA, and EXB bit are present in channel B only and point to the ISTA (CHA),
EXIR (CHA), and EXIR (CHB) registers.
After the HSCX has requested an interrupt by turning its INT pin to low, the CPU must
first read the ISTA register of channel B and check the state of these bits in order to
determine which interrupt source(s) of which channel(s) has caused the interrupt. More
than one interrupt source may be indicated by a single interrupt request.
After the respective register has been read, EXA, and EXB are reset. All other bits will be
reset after reading ISTA. To prevent malfunctions, each bit is individually monitored and
reset.
To generate edges at the INT pin it is necessary to mask all interrupts at the end of the
interrupt service routine and write back the old mask to the mask register.
Mask Register (WRITE)
7
0
MASK
RME
RPF
RSC
XPR
TIN
ICA
EXA
EXB
(20/60)
Value after RESET: 00H (all interrupts enabled)
Each interrupt source can be selectively masked by setting the respective bit in MASK (bit
positions corresponding to ISTA register). Masked interrupts are not indicated when reading
ISTA. Instead, they remain internally stored and will be indicated after the respective MASK bit
is reset.
Note: In the event of an extended interrupt, no interrupt request will be generated with a
masked EXA, EXB bit, although this bit is set in ISTA.
Semiconductor Group
83
INFINEON [ Infineon ]
