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PEB2091NV5.3 参数 Datasheet PDF下载

PEB2091NV5.3图片预览
型号: PEB2091NV5.3
PDF下载: 下载PDF文件 查看货源
内容描述: 集成电路通信( ISDN Echocancellation电路) [ICs for Communications(ISDN Echocancellation Circuit)]
分类和应用: 电信集成电路综合业务数字网通信
文件页数/大小: 299 页 / 1531 K
品牌: INFINEON [ Infineon ]
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PEB 2091  
PEF 2091  
Functional Description  
Superframe  
5
Receive  
U Frame  
1 isw  
2
3
4
6
7
8
1
Superframe  
Marker  
IOM R Frame  
12  
24  
36  
32  
48  
60  
72  
84  
80  
96  
No  
No  
1
49  
Possible Start of  
Monitor Procedure  
Start of  
New  
Transfer  
Start of  
New  
Transfer  
Reset  
Reset  
ITD04232  
Figure 30  
Monitor Access with MTO Enabled  
Monitor Channel Transmitter and MTO Enabled  
The transmitter is reset in 6 ms intervals in the frames shown above. In case the  
transmission of a monitor message has not been completed before the transmitter is  
reset, the complete message will be lost. A message that has been lost due to the  
interruption of a monitor reset will not be retransmitted.  
To prevent this loss of monitor messages, the IEC-Q will only commence a monitor  
transmission if more than 16 IOM®-2 frames will be available for transmission before the  
next reset occurs. Transmission thus does not start during frame numbers 33 … 48 and  
81 … 96. To ensure correct transmission the receiver must not delay the receive  
procedure for more than the following value:  
• 2-byte transmission: max. speed = 8 frames => max. controller (receive) delay =  
8 frames.  
Monitor Channel Receiver and MTO Enabled  
The receiver is reset in 6 ms intervals in the frames shown above. In case the reception  
of a monitor message has not been completed before the receiver is reset, the complete  
message can be lost because the generation of an abort request can not be guaranteed.  
To prevent this loss of monitor messages the PEB 2091 will only commence a monitor  
reception (i.e. acknowledge the 1st received byte) if more than 16 IOM®-2 frames will be  
available for reception before the next reset occurs. Reception thus does not start during  
frame numbers 33 … 48 and 81 … 96. To ensure correct reception, the transmitter must  
not delay the receive procedure for more than the following value:  
• 2-byte reception: max. speed = 7 frames => max. controller (transmit) delay = 9  
frames.  
Semiconductor Group  
81  
Data Sheet 01.99  
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