PEB 2091
PEF 2091
Functional Description
3.7.1
LT Mode
U
XIN
Interface
FSC
DCL
LT
LT
1
U
XIN
Interface
FSC
DCL
2
15.36 MHz
8 kHz
PTT Ref. Clock
PLL
%
512-4096 kHz
U
XIN
Interface
FSC
DCL
LT
8
Synchr.
Downstream
(
)
Figure 32
Clock Generation for LT Mode
The LT mode is typically chosen for ISDN-line card applications. The U transceiver has
to synchronize onto an externally provided PTT-master clock. A phase locked loop (PLL)
is required to generate the IOM®-2 clock signals FSC (Frame Synchronization) and DCL
(Data Clock) as well as the 15.36 MHz IEC-Q master clock.
XIN/XOUT
Pin XOUT should be left open.
The synchronized 15.36 MHz clock should be provided on pin XIN. A synchronized
IEC-Q system clock guarantees that U-interface transmission will be synchronous to the
PTT-master clock.
Semiconductor Group
84
Data Sheet 01.99
INFINEON [ Infineon ]
