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PEB2091NV5.3 参数 Datasheet PDF下载

PEB2091NV5.3图片预览
型号: PEB2091NV5.3
PDF下载: 下载PDF文件 查看货源
内容描述: 集成电路通信( ISDN Echocancellation电路) [ICs for Communications(ISDN Echocancellation Circuit)]
分类和应用: 电信集成电路综合业务数字网通信
文件页数/大小: 299 页 / 1531 K
品牌: INFINEON [ Infineon ]
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PEB 2091  
PEF 2091  
Functional Description  
The check digits (CRC bits CRC1, CRC2, …, CRC12) generated are transmitted at  
position M5 and M6 in the U-superframe (see "U-Frame Structure", page 68). At the  
receiving side this value is compared with the value calculated from the received  
superframe.  
In case these values are not identical a CRC-error will be indicated to both sides of the  
U-interface. In chapter 4.5, page 176, different methods of monitoring transmission  
quality are discussed in detail.  
3.4.2  
Receiver  
The Receiver block (REC) performs the filter algorithmic functions using digital signal  
processing techniques. Modules for echo cancellation, pre- and post-equalization,  
phase adaptation and frame detection are implemented in a modular multi-processor  
concept.  
3.4.3  
Line Interface Unit  
The Line Interface Unit (LIU) contains the crystal oscillator and all of the analog  
functions, such as the A/D-converter and the awake unit in the receive path, the  
pulse-shaping D/A-converter, and the line driver in the transmit path. Furthermore it  
provides an analog test loop-back function. Refer also to "Analog Characteristics", page  
266 for detailed information about the electrical characteristics of the LIU.  
Analog-to-Digital Converter  
The ADC was especially developed for the IEC-Q. It is a sigma-delta modulator of  
second order using a clock rate of 15.36-MHz.  
The peak input signal measured between AIN and BIN must be below 4 Vpp. In case the  
signal input is too low (long range), the received signal is amplified internally by 6 dB.  
The maximum signal to noise ratio is achieved with 1.3 Vpp (long range) and 2.6 Vpp  
(short range) input signal voltage.  
The impedance measured between AIN and BIN is at least 50 k.  
Awake Block  
The Awake circuit evaluates the differential signal between AIN and BIN. The differential  
threshold level is between 4 mV and 28 mV. The DC-level (common mode level) may be  
between 0 V and 3 V. Level detect is not effected by the range setting.  
Digital-to-Analog Converter  
The output pulse is shaped by a special DAC. The DAC was optimized for excellent  
matching between positive and negative pulses and high linearity. It uses a fully  
differential capacitor approach. The staircase-like output signal of the DAC drives the  
Semiconductor Group  
65  
Data Sheet 01.99