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PEB2091NV5.3 参数 Datasheet PDF下载

PEB2091NV5.3图片预览
型号: PEB2091NV5.3
PDF下载: 下载PDF文件 查看货源
内容描述: 集成电路通信( ISDN Echocancellation电路) [ICs for Communications(ISDN Echocancellation Circuit)]
分类和应用: 电信集成电路综合业务数字网通信
文件页数/大小: 299 页 / 1531 K
品牌: INFINEON [ Infineon ]
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PEB 2091  
PEF 2091  
Functional Description  
Control Block  
Complete activation and deactivation procedures are implemented, which are controlled  
by activation and deactivation indications from U, IOM®-2 or µP interfaces. State  
transition of the procedures depend on the actual status of the Receiver (adaptation and  
synchronization) and timing functions to watch fault conditions.  
Embedded Operational Channel (EOC) Processor  
Two different modes can be selected for maintenance functions: In the Auto mode all  
EOC procedure handling and executing as specified by ANSI is performed. In the  
Transparent mode all bits are transferred transparently to the user’s interfaces without  
any internal processing.  
See "Embedded Operations Channel (EOC)", page 69 for definition, and "Access to  
EOC of U-Interface", page 110 for informations about programming and monitoring the  
EOC.  
Single Bits (SB) Processor  
The single bits are used mainly to communicate status and maintenance functions  
between the transceivers. The meaning of a bit position depends upon the direction of  
transmission (upstream/downstream) and the operation mode (repeater or NT/LT). The  
SB processor interprets these bits and gives access to some of them according to the  
mode used. It also provides several filtering methods for SB indications.  
See "Single Bits Channel", page 69 for definition, and "Access to the Single Bits of  
U-Interface", page 115 for informations about programming and monitoring the SB.  
Special Functions (SF)  
This block provides miscellaneous functions of the SIU, like the power controller function  
in stand-alone mode, access to internal chip data, test loops control, S/G bit control in  
µP mode and others. These will be discussed in detail in chapter 4.  
Cyclic Redundancy Check (CRC)  
The cyclic redundancy check provides a possibility to verify the correct transmission of  
data. The check sum of a transmitted U-superframe is calculated from the bits in the  
D-channel, both B-channels, and the M4 bits according to the CRC polynomial  
G (u) = u12 + u11 + u3 + u2 + u + 1  
(+ modulo 2 addition)  
Semiconductor Group  
64  
Data Sheet 01.99  
 
 
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