Functional Description
– Digital exchange applications (LT-S/LT-T) as a full duplex time-multiplexed connection to
convey the B channels between the S/T interface and a Peripheral Board Controller (e.g.
PBC PEB 2050 or PIC PEB 2052), which performs time-slot assignment on the PCM
highways, forming a system interface to a switching network (figure 18).
Timing mode 1 (SPCR:SPM=1) has to be programmed, hence SLD operates in slave mode.
S
SLD
FSC2
FSD
SIP
512 kbit/s
SIPX
SCL
SYP
System Interface
PCM Highway
ISAC R -S
Timing
Mode 1
512 kHz
8 kHz
DCL
PBC
CLK
FSC1
LT-S/LT-T
SLD OUT
SLD IN
SIP
B1 B2 FC SIG B1 B2 FC SIG
FSC1
1/8 Frame Period
FSD
ITS00859
Figure 18
Connection of the ISAC®-S as B-Channel Source/Destination to a Peripheral Board
Controller via SLD, in Timing Mode 1
The µC system has access to B-channel data via the ISAC-S registers:
– C1R (35 ), C2R (36 )
→
B1/B2
H
H
The µP access to C1R and C2R must be synchronized to the serial transmission by means of
Synchronous Transfer Interrupt (STCR) and the BVS bit (STAR) (see chapter 2.3.6).
Semiconductor Group
45
INFINEON [ Infineon ]
