Functional Description
Timing Mode 0 (SPM = 0)
In timing mode 0 the SLD operates in master mode and the SSI (Serial Port A) is operational;
pin SCA/FSD delivers a 128-kHz clock (SCA). The IOM, SLD and SSI interface frame begin is
at the same point in time i.e. at the rising edge of FSC1,2 (ADF1:FC2,1=0).
In TE mode, it is mandatory to program timing mode 0. The polarity of the symmetrical 8-kHz
output signals FSC1 and FSC2 can be independently selected via ADF1:FC2, 1.
In LT-T and LT-S modes, timing mode 0 may be programmed if the SLD master mode and/
or the SSI interface is required.
In these cases FSC1 and FSC2 (inputs) should both be connected to the same 8-kHz frame
sync signal (see figure 14).
IOM R -2
R
IOM
IDP1
Compatible
TE Mode
IDP0
ISAC R -S
Timing Mode 0
Communications
Controller
DCL
FSC1/2
IOM R -2
IDP1
IDP0
R
IOM
LT-T, LT-S Mode
Timing Mode 0
Compatible
Controller
ISAC R -S
DCL
FSC1
FSC2
FSC (Syst.)
CLK (Syst.)
FSC1/2
(ADF1 : FC2,1 = 00)
IOM R Frame
SLD/SSI Frames
ITS00853
Figure 14
IOM®-1 Interface Signals/Timing Mode 0
Semiconductor Group
41
INFINEON [ Infineon ]
