Functional Description
Table 3
µP Access to B Channels (IOM®-1)
C×R
B×CR
Read
IOM
IOM
IOM
–
CxC1
CxC0
Read
SLD
SLD
SSI
Write
SLD
–
Application(s)
0
0
1
1
0
1
0
1
B× not switched, SLD looping
B× switched to/from SLD
B× switched to/from SSI
IOM looping
–
IOM
IOM
Note: x = 1 for channel 1 or 2 for channel 2
The Synchronous Transfer Interrupt (SIN, ISTA register) can be programmed to occur at either
the beginning of a 125 µs frame or at its center, depending on the channel (s) to be accessed
and the current configuration, see figure 22.
(a) CxC1, CxC0 = 00, SLD Loop
R
SIP
SLD
IOM
IDP0
BxCR
CxR
µP
FSC
BVS
IDP0
B1
B2
B1
SLD
B1
B2
B1
B2
B1
B2
OUT
IN
ITS00864
SIN(ST0)
µP Access
Figure 22
Bx Channel Access
Semiconductor Group
49
INFINEON [ Infineon ]
