Operational Description
Register (address) Bit
Effect
Application Restricted to
ADF1
(38 )
H
TEM
Test Mode
Tests with
layer
1 disabled
CFS
0 Permanent standby
1 Power down state
enabled
TE
IOM-1
LT-S/NT
0 S-interface point-to-point
1 S-bus configuration
PFS
Prefilter enable
TE/LT-T
non-TE
CSEL2-0 IOM channel select (time
slot)
IOM-2
IOF
FC1-2
IOM OFF/ON
Polarity of FSC1/2
TE
TE
IOM-2
IOM-1
CIX0
(31 )
H
RSS
Hardware reset generated
by either subscriber/
exchange awake or
watchdog timer
TE specific
functions
(TSF = 1)
STCR
(37 )
H
TSF
Terminal specific function
enable/SLD interface enable
TBA2-0 TIC bus address
Bus
configuration
for D + C/I
(TIC)
MODE
(22 )
H
MDS2-0 HDLC message transfer
mode 2 bytes/1 byte address
TMD
Timer mode
external/internal
Auto mode
only
DIM2-0
Point-to-point/TIC bus
configuration on IOM
interface, for D + C/I channel
arbitration
Point-to-point/bus
configuration on S/T
interface, for D-channel
access.
Semiconductor Group
193
INFINEON [ Infineon ]
