Register Description
4
Detailed Register Description
The parameterization of the ISAC-S and the transfer of data and control information between
the µP and ISAC-S is performed through two register sets.
The register set in the address range 00-2B pertains to the HDLC transceiver and LAPD
H
controller. It includes the two FIFOs having an identical address range from 00-1F .
H
The register set ranging from 30-3B pertains to the control of layer-1 functions and of the IOM
H
interface. Since the meaning of most register bits depends on the selected IOM mode (IOM-1
or IOM-2), the description of this register set is divided into two sections:
● 4.2 Special Purpose Registers: IOM-1 Mode
● 4.3 Special Purpose Registers: IOM-2 Mode
The address map and a register summary are shown in the following tables:
Table 20
ISAC®-S Address Map 00-2B
H
Address Read
(hex)
Write
Name
Description
Name Description
XFIFO Transmit FIFO
00
.
.
RFIFO Receive FIFO
1F
20
21
22
23
24
ISTA
Interrupt Status Register
Status Register
MASK Mask Register
STAR
CMDR Command Register
MODE Mode Register
TIMR
EXIR
Timer Register
Extended Interrupt
Register
XAD1
XAD2
Transmit Address 1
Transmit Address 2
25
RBCL
Receive Frame Byte Count
Low
26
27
28
29
2A
SAPR
RSTA
Received SAPI
SAP1
SAP2
TEI1
Individual SAPI 1
Individual SAPI 2
Individual TEI 1
Individual TEI 2
Receive Status Register
RHCR Receive HDLC Control
TEI2
RBCH Receive Frame Byte Count
High
2B
STAR2 Status Register 2
Semiconductor Group
195
INFINEON [ Infineon ]
