Operational Description
by RMC, the corresponding interrupt will be generated only when RMC has been issued. When
RME has been indicated, bits 0-4 of the RBCL register represent the number of bytes stored
in the RFIFO. Bits 7-5 of RBCL and bits 0 to 3 of RBCH indicate the total number of 32-byte
blocks which where stored until the reception of the remainder block.
The contents of RBCL, RBCH and RSTA registers are valid only after the occurrence of the
RME interrupt, and remain valid until the microprocessor issues an acknowledgement (RMC).
The contents of RHCR and/or SAPR, also remain valid until acknowledgement.
If a frame could not be stored due to a full RFIFO, the microcontroller is informed of this via the
Receive Frame Overflow interrupt (RFO)
3.4.2
HDLC Frame Transmission
After the XFIFO status has been checked by polling the Transmit FIFO Write Enable (XFW) bit
or after a Transmit Pool Ready (XPR) interrupt, up to 32 bytes may be entered in XFIFO.
Transmission of an HDLC frame is started when a transmit command (see table 17) is issued.
The opening flag is generated automatically. In the case of an auto mode transmission (XIF or
XIFC), the control field is also generated by the ISAC-S, and the contents of register XAD1
(and, for LAPD, XAD2) are transmitted as the address, as shown in figure 81.
HDLC Frame
Flag
Flag
Flag
Flag
Address
XAD1
Control
Control
Control
Information
XFIFO
CRC
CRC
CRC
CRC
Flag
Flag
Flag
Flag
Transmit I-Frame
(XIF)
Auto Mode, 8-Bit Addr.
Transmit I-Frame
(XIF)
Auto-Mode, 16-Bit Addr.
XAD1 XAD2
XFIFO
Transmit Transparent
Frame (XTF)
XFIFO
All Modes
Note: Length of Control Field is b or 16 Bit
Description of Symbols:
Generated automatically by ISAC R -S
Written initially by CPU (Info Register)
Loaded (repeatedly) by CPU upon ISAC R -S
request (XPR Interrupt)
ITD02341
Figure 81
Transmit Data Flow
Semiconductor Group
189
INFINEON [ Infineon ]
