Operational Description
Register (address) Bit
Effect
Application Restricted to
TIMR
(23 )
H
CNT
VALUE
N1 and T1 in internal timer
mode (TMD = 1)
T2 in external timer mode
XAD1
XAD2
(24 )
H
(25 )
H
SAPI, TEI
Transmit frame address
Auto mode
only
SAP1/2 (26 /27 )
Receive SAPI, TEI address
values for internal address
recognition
H
H
TEI1/2
(28 /29 )
H H
Note: After a hardware reset the pins SDAX/SDS1 and SCA/FSD/SDS2 are both "low" and
have the functions of SDS1 and SDS2 in terminal timing mode (since SPM=0), respec-
tively, until the SPCR is written to for the first time. From that moment on, the function
taken on by these pins depends on the state of the IOM Mode Select bit IMS (ADF2
register).
Semiconductor Group
194
INFINEON [ Infineon ]
