Operational Description
3.4.1
HDLC Frame Reception
Assuming a normally running communication link (layer-1 activated, layer-2 link established,
TEI assigned), figure 79 illustrates the transfer of an I-frame via the D channel. The transmitter
is shown on the left and the receiver on the right, with the interaction between the
microcontroller system and the ISAC-S in terms of interrupt and command stimuli.
When the frame (excluding the CRC field) is not longer than 32 bytes, the whole frame is
transferred in one block. The reception of the frame is reported via the Receive Message End
(RME) interrupt. The number of bytes stored in RFIFO can be read out from RBCL. The
Receive Status Register (RSTA) includes information about the frame, such as frame aborted
yes/no or CRC valid yes/no and, if complete or partial address recognition is selected, the
identification of the frame address.
Depending on the HDLC message transfer mode, the address and control field of the frame
can be read from auxiliary registers (SAPR and RHCR), as shown in figure 80.
LAPD Link
RPF
XIF/XTF
XPR
I-Frame
RMC
RPF
ISAC R -S
(TE)
ISAC R -S
(LT-S)
µC-
System
XIF/XTF
µC-
System
XPR
RMC
RME
XIFC/XTFC
)
*
S-Frame
(RR)
(Transparent
XPR
Transmit)
(Auto Mode
Transmit)
XPR
RMC
:=
ITD02391
Data Transfer *) In Auto Mode the "RR" Response will be Transmitted Autonomously
Figure 79
Transmission of an I-Frame in the D Channel (Subscriber to Exchange)
Semiconductor Group
187
INFINEON [ Infineon ]
