Operational Description
Address
High
Address
Low
Flag
Control
Information
RFIFO
CRC
Flag
SAP1, SAP2
FE, FC
TEI1, TEI2
FF
Auto Mode
-
(U-and FraΙm- es)
RHCR
RSTA
(Note 1)
(Note 2)
(Note 3)
SAP1, SAP2
FE, FC
TEI1, TEI2
FF
Non-Auto
Mode
RHCR
RFIFO
RFIFO
RSTA
RSTA
(Note 1)
(Note 2)
(Note 4)
TEI1, TEI2
FF
Transparent
Mode 1
SAPR
RHCR
(Note 4)
Transparent
Mode 2
RFIFO
RSTA
RSTA
SAP1, SAP2
FE, FC
Transparent
Mode 3
RFIFO
Description of Symbols:
Checked automatically by ISAC R -S
Compared with Register or Fixed Value
Stored Info Register or RFIFO
ITD02342
Figure 80
Receive Data Flow
Note 1 Only if a 2-byte address field is defined (MDS0 = 1 in MODE register).
Note 2 Comparison with Group TEI (FF ) is only made if a 2-byte address field is defined
H
(MDS0 = 1 in MODE register).
Note 3 In the case of an extended, modulo 128 control field format (MCS = 1 in SAP2
register) the control field is stored in RHCR in compressed form (I frames).
Note 4 In the case of an extended control field, only the first byte is stored in RHCR, the
second in RFIFO.
A frame longer than 32 bytes is transferred to the microcontroller in blocks of 32 bytes plus one
remainder block of length 1 to 32 bytes. The reception of a 32-byte block is reported by a
Receive Pool Full (RPF) interrupt and the data in RFIFO remains valid until this interrupt is
acknowledged (RMC). This process is repeated until the reception of the remainder block is
completed, as reported by RME (figure 79). When the total frame length exceeds 4095 bytes,
bit OV (RBCH) is set but the counter is not blocked. If the second RFIFO pool has been filled
or an end-of-frame is received while a previous RPF or RME interrupt is not yet acknowledged
Semiconductor Group
188
INFINEON [ Infineon ]
