Operational Description
3.4
Control of Layer-2 Data Transfer
The control of the data transfer phase is mainly done by commands from the µP to ISAC-S via
the Command Register (CMDR).
Table 16 gives a summary of possible interrupts from the HDLC controller and the appropriate
reaction to these interrupts.
Table 17 lists the most important commands which are issued by a microprocessor by setting
one or several bits in CMDR.
The powerful FIFO logic, which consists of a 2 × 32 byte receive and 2 × 32 byte transmit FIFO,
as well as an intelligent FIFO controller, builds a flexible interface to the upper protocol layers
implemented in the microcontroller.
The extent of LAPD protocol support is dependent on the selected message transfer mode,
see section 2.4.2.
Table 16
Interrupts from ISAC®-S HDLC Controller
Mnemonic Register
(addr. hex)
Meaning
Reaction
Layer-2 Receive
RPF
ISTA (20) Receive Pool Full. Request to
read received bytes of an
uncompleted HDLC frame from
RFIFO
Read 32 bytes from RFIFO and
acknowledge with RMC.
RME
ISTA (20) Receive Message End. Request Read RFIFO (number of bytes
to read received bytes of a
complete HDLC frame (or the
given by RBCL4-0) and status
information and acknowledge
last part of a frame) from RFIFO. with RMC.
RFO
PCE
EXIR (24) Receive Frame Overflow. A
Error report for statistical
purposes. Possible cause:
deficiency in software.
complete frame has been lost
because storage space in
RFIFO was not available.
EXIR (24) Protocol Error. S or I-frame with Link re-establishment.
incorrect N(R) or S frame with
I-field received (in auto mode
only) or an I-frame which is not a
command or
Indication to layer 3.
S-frame with an undefined
control field.
Semiconductor Group
184
INFINEON [ Infineon ]
