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ICE3BS02 参数 Datasheet PDF下载

ICE3BS02图片预览
型号: ICE3BS02
PDF下载: 下载PDF文件 查看货源
内容描述: 离线式开关电源电流模式控制器,集成500V启动电池 [Off-Line SMPS Current Mode Controller with integrated 500V Startup Cell]
分类和应用: 稳压器开关式稳压器或控制器电源电路电池开关式控制器光电二极管
文件页数/大小: 23 页 / 486 K
品牌: INFINEON [ Infineon ]
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F3  
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G  
Functional Description  
The Gate Driver is active low at voltages below the  
3.4  
PWM Section  
undervoltage lockout threshold VVCCoff  
.
0.72  
PWM Section  
Oscillator  
VCC  
Duty  
Cycle  
max  
PWM-Latch  
1
Clock  
Gate  
Z1  
Gate  
Soft Start  
FF1  
Q
Driver  
Comparator  
S
R
1
&
PWM  
G8  
Comparator  
G9  
Figure 8  
Gate Driver  
Current  
Limiting  
The driver-stage is optimized to minimize EMI and to  
provide high circuit efficiency. This is done by reducing  
the switch on slope when exceeding the external  
Power Switch threshold. This is achieved by a slope  
control of the rising edge at the driver’s output (see  
Figure 9).  
Gate  
Figure 7  
PWM Section  
ca. t = 130ns  
VGate  
3.4.1  
Oscillator  
The oscillator generates  
a fixed frequency. The  
switching frequency for ICE3AS02/G is fOSC = 100kHz  
and for ICE3BS02/G fOSC = 67kHz. A resistor, a  
capacitor and a current source and current sink which  
determine the frequency are integrated. The charging  
and discharging current of the implemented oscillator  
capacitor are internally trimmed, in order to achieve a  
very accurate switching frequency. The ratio of  
controlled charge to discharge current is adjusted to  
reach a maximum duty cycle limitation of Dmax=0.72.  
CLoad = 1nF  
5V  
t
Figure 9  
Gate Rising Slope  
Thus the leading switch on spike is minimized. When  
the external Power Switch is switched off, the falling  
shape of the driver is slowed down when reaching 2V  
to prevent an overshoot below ground. Furthermore the  
driver circuit is designed to eliminate cross conduction  
of the output stage. During powerup when VCC is  
below the undervoltage lockout threshold VVCCoff, the  
output of the Gate Driver is low to disable power  
transfer to the seconding side.  
3.4.2  
PWM-Latch FF1  
The oscillator clock output provides a set pulse to the  
PWM-Latch when initiating the external Power Switch  
conduction. After setting the PWM-Latch can be reset  
by the PWM comparator, the Soft Start comparator or  
the Current-Limit comparator. In case of resetting, the  
driver is shut down immediately.  
3.4.3  
Gate Driver  
The Gate Driver is a fast totem pole gate drive which is  
designed to avoid cross conduction currents and which  
is equipped with a zener diode Z1 (see Figure 8) in  
order to improve the control of the Gate attached power  
transistors as well as to protect them against  
undesirable gate overvoltages.  
Version 1.1  
10  
21 May 2004  
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